Ben Lancaster
CPU Design Engineer @ Arm
Experience
Senior CPU Design Engineer
Arm - Processor Design Group — Cambridge, UK — 2022-Present
- Released products - Cortex-A520AE, Cortex-A725, DSU-120, C1-Pro, C1-DSU.
- RTL designer on the DSU project - an Armv9 distributed CPU L3 memory system supporting multi-core CPU clusters.
- Owned microarchitecture, specification, for various CPU functional blocks targeting high frequency (4GHz+), low-power, low-area, on the latest TSMC technology nodes (3nm).
- Responsible for power/clock/reset design for all Arm Cortex A-class CPUs. Experienced in CDC/RDC analysis.
- Design investigation for various new Armv9-A architectural features (Scalable Matrix Extension 2, RME, GICv5).
- Improved dynamic power for CHI interconnect with a novel async fifo mechanism to pass critical routing information one cycle ahead of the main payload.
- Extending CPU designs to support ASIL B/D (ISO 26262) and Dual-Core Lock Step for automotive applications.
- Experienced with UPF for multi-core CPU clusters with many power domains, power states, and crossings.
Interconnect RTL Design Engineer
Arm - Interconnect Group — Cambridge, UK — 2019-2022
- Released products - CoreLink NI-700, SI-L1
- Owned multiple units for a System Level Cache IP - Memory System Filtering unit, RAS, Performance Monitoring unit.
- Experienced with AMBA CHI and AXI-5 interfaces. Updating memory interfaces to support newer features.
- Collaboration with Verification, Physical Design, Architecture, and DFT teams throughout the project life cycle.
- Experienced with Network-on-chip and Mesh interconnects for scalable many-core designs.
Firmware Engineer, Intern
Spirent Communications - Positioning Group — Paignton, UK — 2016-2017
- Released products - GSS7000, GSS9000
- Mixed-signal design for software-defined multi-frequency GNSS signal generators using Xilinx UltraScale FPGAs.
- Implemented algorithm for dynamic power attenuation/calibration using programmable DACs for consistent signal power.
- Experience using various test equipment (oscilloscopes, spectrum analyzers, function generators, power meters).
Education
MSc(Eng) Embedded Systems Engineering
University of Leeds — United Kingdom — 2018-2019
- Pass with Distinction ~86%
- Final Project: Multi-core CPU Design and Implementation for FPGAs
- FPGA Design for System-on-Chip
- Digital Signal Processing for Communications
- Embedded Systems
- Signals and Systems
- Control Systems
- Microprocessor System Design
BSc (Hons) Computer Science
University of Plymouth — United Kingdom — 2014-2018
- Awards: Top Final Student in Computing, Best Final Project
- First Class Honours with Certificate of Professional Industrial Experience
- Final Project: FPGA-based 16-bit RISC CPU Design
- Revell Research Systems Prize Winner
Open Source Projects
Out-of-order RV32IMC CPU
bendl/riscy-oooComing soon...
Multi-core RISC CPU Design
bendl/vmicro16Multi-core RISC SoC with various peripherals including: watchdogs, timer interrupts, GPIO, UART, and more.
FPGA 16-bit Embedded CPU Design
bendl/prco304/prco_core16-bit RISC processor design and implementation for Xilinx Spartan-6 FPGAs featuring pipelining, on-chip memory, GPIO, and UART modules.
PCB development board for Arm Cortex-M0
bendl/armm0A 2-layer board for the Minispartan6+ FPGA development kit. Features an STM32F0 TSSOP processor, mutliple power supplies, I2C, ICSP, and LEDs.
FPGA and JTAG Development Board
bendl/osc1PCB board for the FT2232H Mini Module and TinyFPGA AX2 for experimenting with JTAG and I2C implementations.
CUDA implementation of Discrete Fourier Transform for GPUs
bendl/soft354Designed, implemented, and evaluated a parallel implementation of the Discrete Fourier Transform.
Read the methodology and results here.
CFG Compiler and Assembler
bendl/prco304/prco_compilerCompiler and assembler for the PRCO embedded processor. Features simple optimisations including constant folding and unreachable code elimination.
Contributions
Gravity Programming Language
marcobambini/gravity — 2.3k starsA dynamic object-oriented programming language, compiler, and virtual machine, implemented in C.
Skills
Digital and Mixed signal design, CPU microarchitecture, Caches, FPGA, SystemVerilog, Low power design.
Hobbies
Tennis, Running, Sailing