Ben Lancaster

CPU Design Engineer @ Arm


ben.lancaster.msc@gmail.com

LinkedIn

github.com/bendl


Contact

Download CV

Experience

Senior Design Engineer

Arm - Processor Design Group — Cambridge, UK — 2019-present

  • Micro-architecture specification and RTL design for A-class CPUs and multi-core clusters for client market targeting smartphones and large screen compute devices.
  • Responsible for power/clock/reset logic for upcoming A-class CPUs featuring multiple power/clock/reset domains and crossings. Experience with CDC and RDC analysis.
  • Extended CPU IP products to support ASIL B/D for automotive and safety critical applications (ISO 26262).
  • Unit design lead for Memory system filtering unit, MPAM, and RAS units for an upcoming System IP.
  • Contributions to design of a fully-coherent L3 System Level Cache using AMBA CHI and AXI5.
  • Created automation flows for generating synthesizable SystemVerilog RTL from machine-readable specifications.
  • Experience implementing AMBA interfaces including CHI, AXI, and APB.

Firmware Engineer, Internship

Spirent Communications - Positioning Group — Paignton, UK — 2016-2017

  • Using Xilinx Virtex UltraScale+/Spartan FPGAs for RF signal generation (GNSS/VHF/UHF).
  • Embedded C programming on Xilinx MicroBlaze and PIC16/24 micro-controllers.
  • Implemented software algorithm for dynamic power attenuation and calibration using programmable DAC for GNSS RF signal generators.
  • Controlling EEPROMs, LEDs, on-board fans, and other peripherals with I2C and SMBus.

Education

MSc(Eng) Embedded Systems Engineering

University of Leeds — United Kingdom — 2018-2019

  • Pass with Distinction ~86%
  • Final Project: Multi-core CPU Design and Implementation for FPGAs
  • FPGA Design for System-on-Chip
  • Embedded Microprocessor System Design
  • Digital Signal Processing for Communications
  • Circuit Analysis
  • Electronics for Medical Devices
  • Secure Hardware Design

BSc (Hons) Computer Science

University of Plymouth — United Kingdom — 2014-2018

  • Awards: Top Final Student in Computing, Best Final Project
  • First Class Honours with Certificate of Professional Industrial Experience
  • Final Project: FPGA-based 16-bit RISC CPU Design
  • Revell Research Systems Prize Winner

Open Source Projects

Out-of-order RV32IMC CPU

bendl/riscy-ooo

Coming soon...

Multi-core RISC CPU Design

bendl/vmicro16

Multi-core RISC SoC with various peripherals including: watchdogs, timer interrupts, GPIO, UART, and more.

FPGA 16-bit Embedded CPU Design

bendl/prco304/prco_core

16-bit RISC processor design and implementation for Xilinx Spartan-6 FPGAs featuring pipelining, on-chip memory, GPIO, and UART modules.

PCB development board for Arm Cortex-M0

bendl/armm0

A 2-layer board for the Minispartan6+ FPGA development kit. Features an STM32F0 TSSOP processor, mutliple power supplies, I2C, ICSP, and LEDs.

FPGA and JTAG Development Board

bendl/osc1

PCB board for the FT2232H Mini Module and TinyFPGA AX2 for experimenting with JTAG and I2C implementations.

CUDA implementation of Discrete Fourier Transform for GPUs

bendl/soft354

Designed, implemented, and evaluated a parallel implementation of the Discrete Fourier Transform.

Read the methodology and results here.

CFG Compiler and Assembler

bendl/prco304/prco_compiler

Compiler and assembler for the PRCO embedded processor. Features simple optimisations including constant folding and unreachable code elimination.

And more on Github...

Contributions

Gravity Programming Language

marcobambini/gravity — 2.3k stars

A dynamic object-oriented programming language, compiler, and virtual machine, implemented in C.

Skills

Verilog, SystemVerilog, FPGA, CPU uarch, ASIC flows, Formal verification, UVM, AMBA

Hobbies

Badminton, Tennis, Skateboarding

Publications